diff options
author | Xander <xander@icth.xyz> | 2023-07-05 23:58:42 +0200 |
---|---|---|
committer | Xander <xander@icth.xyz> | 2023-07-05 23:58:42 +0200 |
commit | cd8a202caac232c7a5b05ad11eb5059d9ad3f002 (patch) | |
tree | 090ba9110b29320dfde7c3eff6ab97f9f548abd8 /kernel/interrupts/idt.sats | |
parent | 5ef9221f4dfe78d69247989ef7edc8d3101a5014 (diff) | |
download | ats-os-cd8a202caac232c7a5b05ad11eb5059d9ad3f002.tar.xz ats-os-cd8a202caac232c7a5b05ad11eb5059d9ad3f002.zip |
Implementing interrupts (exceptions)
Diffstat (limited to 'kernel/interrupts/idt.sats')
-rw-r--r-- | kernel/interrupts/idt.sats | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/kernel/interrupts/idt.sats b/kernel/interrupts/idt.sats new file mode 100644 index 0000000..d8391aa --- /dev/null +++ b/kernel/interrupts/idt.sats @@ -0,0 +1,29 @@ + +#define +TRAP_GATE_FLAGS 0x8F // p=1, dpl=0b00, type=0b1111 + +typedef idt_entry_t = @{ + isr_low = uint16, // The lower 16 bits of the ISR's address + kernel_cs = uint16, // The GDT segment selector that the CPU will load into CS before calling the ISR + ist = uint8, // The IST in the TSS that the CPU will load into RSP; set to zero for now + attributes = uint8, // Type and attributes; see the IDT page + isr_mid = uint16, // The higher 16 bits of the lower 32 bits of the ISR's address + isr_high = uint32, // The higher 32 bits of the ISR's address + reserved = uint32 // Set to zero +} + +typedef idtr_t = @{ + limit = uint16, + base = uint64 +} + +// Interrupt frame to pass to ISR +typedef int_frame = @{ + ip = uint64, // instruction pointer + cs = uint64, // code segment + rflags = uint64, + sp = uint64, // stack pointer + ss = uint64 // stack segment +} + +fun idt_init() : void |