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authorXander <xander@icth.xyz>2023-07-07 16:07:49 +0200
committerXander <xander@icth.xyz>2023-07-07 16:07:49 +0200
commitb14f83f53dfb1f4bf1b5eeb8162891a9aeeaff1c (patch)
tree402bfe2a7702e29be97ea479aadacdcdcbf6635f /kernel/interrupts/idt.sats
parentcd8a202caac232c7a5b05ad11eb5059d9ad3f002 (diff)
downloadats-os-b14f83f53dfb1f4bf1b5eeb8162891a9aeeaff1c.tar.xz
ats-os-b14f83f53dfb1f4bf1b5eeb8162891a9aeeaff1c.zip
Default interrupts
Diffstat (limited to 'kernel/interrupts/idt.sats')
-rw-r--r--kernel/interrupts/idt.sats9
1 files changed, 5 insertions, 4 deletions
diff --git a/kernel/interrupts/idt.sats b/kernel/interrupts/idt.sats
index d8391aa..ce40cd8 100644
--- a/kernel/interrupts/idt.sats
+++ b/kernel/interrupts/idt.sats
@@ -1,20 +1,21 @@
-
#define
TRAP_GATE_FLAGS 0x8F // p=1, dpl=0b00, type=0b1111
+#define
+INT_GATE_FLAGS 0x8E // p=1, dpl=0b00, type=0b1110
typedef idt_entry_t = @{
isr_low = uint16, // The lower 16 bits of the ISR's address
kernel_cs = uint16, // The GDT segment selector that the CPU will load into CS before calling the ISR
- ist = uint8, // The IST in the TSS that the CPU will load into RSP; set to zero for now
+ ist = uint8 0, // The IST in the TSS that the CPU will load into RSP; set to zero for now
attributes = uint8, // Type and attributes; see the IDT page
isr_mid = uint16, // The higher 16 bits of the lower 32 bits of the ISR's address
isr_high = uint32, // The higher 32 bits of the ISR's address
- reserved = uint32 // Set to zero
+ reserved = uint32 0 // Set to zero
}
typedef idtr_t = @{
limit = uint16,
- base = uint64
+ base = [l : addr] ptr l
}
// Interrupt frame to pass to ISR